Microchip Technology MA330019-2 数据表

DS70292G-page 16

© 2007-2012 Microchip Technology Inc.

SCL1
SDA1
ASCL1
ASDA1

I/O
I/O
I/O
I/O

ST
ST
ST
ST

No
No
No
No

Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.

TMS

TCK

TDI

TDO

I
I
I

O

ST
ST
ST

—

No
No
No
No

JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.

C1RX 
C1TX

I

O

ST

—

Yes
Yes

ECAN1 bus receive pin.
ECAN1 bus transmit pin. 

RTCC 

O

—

No

Real-Time Clock Alarm Output.

CV

REF

O

ANA

No

Comparator Voltage Reference Output.

C1IN-  
C1IN+  
C1OUT

I
I

O

ANA
ANA

—

No
No

Yes

Comparator 1 Negative Input.
Comparator 1 Positive Input.
Comparator 1 Output.

C2IN- 
C2IN+ 
C2OUT  

I
I

O

ANA
ANA

—

No
No

Yes

Comparator 2 Negative Input.
Comparator 2 Positive Input.
Comparator 2 Output.

PMA0          

PMA1

PMA2 -PMPA10
PMBE 
PMCS1
PMD0-PMPD7

PMRD
PMWR      

I/O

I/O 

O
O
O

I/O

O
O

TTL/ST

TTL/ST

—
—
—

TTL/ST

—
—

No

No

No
No
No
No

No
No

Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and 
Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and 
Output (Master modes).
Parallel Master Port Address (Demultiplexed Master Modes).
Parallel Master Port Byte Enable Strobe.
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.

DAC1RN  

DAC1RP 

DAC1RM 

O
O
O

—
—
—

No
No
No

DAC1 Right Channel Negative Output.
DAC1 Right Channel Positive Output.
DAC1 Right Channel Middle Point Value (typically 1.65V).

DAC1LN  

DAC1LP 

DAC1LM 

O
O
O

—
—
—

No
No
No

DAC1 Left Channel Negative Output.
DAC1 Left Channel Positive Output.
DAC1 Left Channel Middle Point Value (typically 1.65V).

COFS

I/O

ST

Yes

Data Converter Interface frame synchronization pin.

CSCK

I/O

ST

Yes

Data Converter Interface serial clock input/output pin.

CSDI

I

ST

Yes

Data Converter Interface serial data input pin

CSDO

O

—

Yes

Data Converter Interface serial data output pin.

PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3

I/O

I

I/O

I

I/O

I

ST
ST
ST
ST
ST
ST

No
No
No
No
No
No

Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.

MCLR

I/P

ST

No

Master Clear (Reset) input. This pin is an active-low Reset to the 
device.

AV

DD

P

P

No

Positive supply for analog modules. This pin must be connected at all 
times.

Legend: CMOS = CMOS compatible input or output

Analog = Analog input

P = Power

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input                      

TTL = TTL input buffer

PPS = Peripheral Pin Select