Microchip Technology MA240029 数据表
2010-2011 Microchip Technology Inc.
DS39996F-page 201
PIC24FJ128GA310 FAMILY
FIGURE 13-2:
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
FIGURE 13-3:
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
T
CY
TCS
(1)
1x
01
TGATE
(1)
00
Gate
T2CK
Sync
PR2 (PR4)
Set T2IF (T4IF)
Equal
Comparator
Reset
Q
Q
D
CK
TGATE
1
0
(T4CK)
Sync
Note
1:
The timer clock input must be assigned to an available RPn/RPIn pin before use. See
for more information.
TMR2 (TMR4)
TON
TCKPS<1:0>
2
T
CY
TCS
(1)
1x
01
TGATE
(1)
00
T3CK
PR3 (PR5)
Set T3IF (T5IF)
Equal
Comparator
TMR3 (TMR5)
Reset
Q
Q
D
CK
TGATE
1
0
A/D Event Trigger
(2)
(T5CK)
Prescaler
1, 8, 64, 256
Sync
Note
1:
for more information.
2:
The A/D event trigger is available only on Timer3.