Microchip Technology MA330013 数据表
dsPIC33F
DS70165E-page 176
Preliminary
©
2007 Microchip Technology Inc.
FIGURE 15-1:
PWM MODULE BLOCK DIAGRAM
PDC4
PDC4 Buffer
PWMCON1
PWMCON2
PTPER
Comparator
Comparator
Channel 4 Dead-Time
Generator and
PTCON
SEVTCMP
Comparator
Special Event Trigger
FLTBCON
OVDCON
PWM Enable and Mode SFRs
PWM Manual
Control SFR
Control SFR
Channel 3 Dead-Time
Generator and
Channel 2 Dead-Time
Generator and
PWM Generator
#3
PWM Generator
#2
PWM Generator #4
SEVTDIR
PTDIR
DTCON1
Dead-Time Control SFRs
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM Generator
#1
Channel 1 Dead-Time
Generator and
Note:
Details of PWM Generator #1, #2 and #3 not shown for clarity.
16
-bit
D
a
ta
Bus
PWM4L
PWM4H
DTCON2
FLTACON
Fault Pin Control SFRs
PWM Time Base
Output
Driver
Block
FLTB
FLTA
Override Logic
Override Logic
Override Logic
Override Logic
Special Event
Postscaler
PTPER Buffer
PTMR