Microchip Technology MA330013 数据表
dsPIC33F
DS70165E-page 268
Preliminary
©
2007 Microchip Technology Inc.
21.3.18
SLOT STATUS BITS
The SLOT<3:0> status bits in the DCISTAT SFR
indicate the current active time slot. These bits will cor-
respond to the value of the frame sync generator
counter. The user may poll these status bits in software
when a DCI interrupt occurs to determine what time slot
data was last received and which time slot data should
be loaded into the TXBUF registers.
indicate the current active time slot. These bits will cor-
respond to the value of the frame sync generator
counter. The user may poll these status bits in software
when a DCI interrupt occurs to determine what time slot
data was last received and which time slot data should
be loaded into the TXBUF registers.
21.3.19
CSDO MODE BIT
The CSDOM control bit controls the behavior of the
CSDO pin during unused transmit slots. A given trans-
mit time slot is unused if it’s corresponding TSEx bit in
the TSCON SFR is cleared.
CSDO pin during unused transmit slots. A given trans-
mit time slot is unused if it’s corresponding TSEx bit in
the TSCON SFR is cleared.
If the CSDOM bit is cleared (default), the CSDO pin will
be low during unused time slot periods. This mode will
be used when there are only two devices attached to
the serial bus.
be low during unused time slot periods. This mode will
be used when there are only two devices attached to
the serial bus.
If the CSDOM bit is set, the CSDO pin will be tri-stated
during unused time slot periods. This mode allows
multiple devices to share the same CSDO line in a
multi-channel application. Each device on the CSDO
line is configured to only transmit data during specific
time slots. No two devices will transmit data during the
same time slot.
during unused time slot periods. This mode allows
multiple devices to share the same CSDO line in a
multi-channel application. Each device on the CSDO
line is configured to only transmit data during specific
time slots. No two devices will transmit data during the
same time slot.
21.3.20
DIGITAL LOOPBACK MODE
Digital Loopback mode is enabled by setting the
DLOOP control bit in the DCICON1 SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin will be ignored in Digital Loopback mode.
DLOOP control bit in the DCICON1 SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin will be ignored in Digital Loopback mode.
21.3.21
UNDERFLOW MODE CONTROL BIT
When an underflow occurs, one of two actions can
occur, depending on the state of the Underflow mode
(UNFM) control bit in the DCICON1 SFR. If the UNFM
bit is cleared (default), the module will transmit ‘
occur, depending on the state of the Underflow mode
(UNFM) control bit in the DCICON1 SFR. If the UNFM
bit is cleared (default), the module will transmit ‘
0
’s on
the CSDO pin during the active time slot for the buffer
location. In this operating mode, the Codec device
attached to the DCI module will simply be fed digital
‘silence’. If the UNFM control bit is set, the module will
transmit the last data written to the buffer location. This
operating mode permits the user to send continuous
data to the Codec device without consuming CPU
overhead.
location. In this operating mode, the Codec device
attached to the DCI module will simply be fed digital
‘silence’. If the UNFM control bit is set, the module will
transmit the last data written to the buffer location. This
operating mode permits the user to send continuous
data to the Codec device without consuming CPU
overhead.
21.4
DCI Module Interrupts
The frequency of DCI module interrupts is dependent
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written TXBUF
values are transferred to the transmit shadow registers
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written TXBUF
values are transferred to the transmit shadow registers
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
21.5
DCI Module Operation During CPU
Sleep and Idle Modes
Sleep and Idle Modes
21.5.1
DCI MODULE OPERATION DURING
CPU SLEEP MODE
CPU SLEEP MODE
The DCI module has the ability to operate while in
Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD =
Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD =
1
). The
DCI module will generate an asynchronous interrupt
when a DCI buffer transfer has completed and the CPU
is in Sleep mode.
when a DCI buffer transfer has completed and the CPU
is in Sleep mode.
21.5.2
DCI MODULE OPERATION DURING
CPU IDLE MODE
CPU IDLE MODE
If the DCISIDL control bit is cleared (default), the mod-
ule will continue to operate normally even in Idle mode.
If the DCISIDL bit is set, the module will halt when Idle
mode is asserted.
ule will continue to operate normally even in Idle mode.
If the DCISIDL bit is set, the module will halt when Idle
mode is asserted.
21.6
AC-Link Mode Operation
The AC-Link protocol is a 256-bit frame with one 16-bit
data slot, followed by twelve 20-bit data slots. The DCI
module has two operating modes for the AC-Link pro-
tocol. These operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> =
data slot, followed by twelve 20-bit data slots. The DCI
module has two operating modes for the AC-Link pro-
tocol. These operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> =
10
. The second
AC-Link mode is called ‘20-bit AC-Link mode’ and is
selected by setting COFSM<1:0> =
selected by setting COFSM<1:0> =
11
.
21.6.1
16-BIT AC-LINK MODE
In the 16-bit AC-Link mode, data word lengths are
restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link proto-
col. For received time slots, the incoming data is simply
truncated to 16 bits. For outgoing time slots, the four
Least Significant bits of the data word are set to ‘
restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link proto-
col. For received time slots, the incoming data is simply
truncated to 16 bits. For outgoing time slots, the four
Least Significant bits of the data word are set to ‘
0
’ by
the module. This truncation of the time slots limits the
ADC and DAC data to 16 bits but permits proper data
alignment in the TXBUF and RXBUF registers. Each
RXBUF and TXBUF register will contain one data time
slot value.
ADC and DAC data to 16 bits but permits proper data
alignment in the TXBUF and RXBUF registers. Each
RXBUF and TXBUF register will contain one data time
slot value.