Microchip Technology MA330011 数据表
dsPIC33F
DS70165E-page 200
Preliminary
©
2007 Microchip Technology Inc.
16.7.2
TIMER OPERATION DURING CPU
IDLE MODE
IDLE MODE
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if QEISIDL (QEICON<13>) =
module is configured in the 16-bit Timer mode, the
16-bit timer will operate if QEISIDL (QEICON<13>) =
0
.
This bit defaults to a logic ‘
0
’ upon executing POR. For
halting the timer module during the CPU Idle mode,
QEISIDL should be set to ‘
QEISIDL should be set to ‘
1
’.
If the QEISIDL bit is cleared, the timer will function
normally as if the CPU Idle mode had not been
entered.
normally as if the CPU Idle mode had not been
entered.
16.8
Quadrature Encoder Interface
Interrupts
Interrupts
The Quadrature Encoder Interface has the ability to
generate an interrupt on occurrence of the following
events:
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
rollover/underflow
• Detection of qualified index pulse or if CNTERR
bit is set
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS3 register.
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS3 register.
Enabling an interrupt is accomplished via the respec-
tive enable bit, QEIIE. The QEIIE bit is located in the
IEC3 register.
tive enable bit, QEIIE. The QEIIE bit is located in the
IEC3 register.
16.9
Control and Status Registers
The QEI module has four user-accessible registers.
The registers are accessible in either Byte or Word
mode. These registers are:
The registers are accessible in either Byte or Word
mode. These registers are:
• Control/Status Register (QEICON) – This register
allows control of the QEI operation and status
flags indicating the module state.
flags indicating the module state.
• Digital Filter Control Register (DFLTCON) – This
register allows control of the digital input filter
operation.
operation.
• Position Count Register (POSCNT) – This loca-
tion allows reading and writing of the 16-bit posi-
tion counter.
tion counter.
• Maximum Count Register (MAXCNT) – The MAX-
CNT register holds a value that will be compared
to the POSCNT counter in some operations.
to the POSCNT counter in some operations.
Note:
The POSCNT register allows byte
accesses, however, reading the register in
byte mode may result in partially updated
values in subsequent reads. Either use
Word mode reads/writes or ensure that
the counter is not counting during byte
operations.
accesses, however, reading the register in
byte mode may result in partially updated
values in subsequent reads. Either use
Word mode reads/writes or ensure that
the counter is not counting during byte
operations.