Microchip Technology MA330011 数据表
©
2007 Microchip Technology Inc.
Preliminary
DS70165E-page 215
dsPIC33F
18.5
I
2
C Module Addresses
The I2CxADD register contains the Slave mode
addresses. The register is a 10-bit register.
addresses. The register is a 10-bit register.
If the A10M bit (I2CxCON<10>) is ‘
0
’, the address is
interpreted by the module as a 7-bit address. When an
address is received, it is compared to the 7 Least
Significant bits of the I2CxADD register.
address is received, it is compared to the 7 Least
Significant bits of the I2CxADD register.
If the A10M bit is ‘
1
’, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value, ‘
compared with the binary value, ‘
11110 A9 A8
’
(where
A9
and
A8
are two Most Significant bits of
I2CxADD). If that value matches, the next address will
be compared with the Least Significant 8 bits of
I2CxADD, as specified in the 10-bit addressing
protocol.
be compared with the Least Significant 8 bits of
I2CxADD, as specified in the 10-bit addressing
protocol.
TABLE 18-1:
7-BIT I
2
C™ SLAVE
ADDRESSES SUPPORTED BY
dsPIC33F
dsPIC33F
18.6
Slave Address Masking
The I2CxMSK register (Register 18-3) designates
address bit positions as “don’t care” for both 7-bit and
10-bit Address modes. Setting a particular bit location
(=
address bit positions as “don’t care” for both 7-bit and
10-bit Address modes. Setting a particular bit location
(=
1
) in the I2CxMSK register, causes the slave module
to respond, whether the corresponding address bit
value is a ‘
value is a ‘
0
’ or ‘
1
’. For example, when I2CxMSK is set
to ‘
00100000
’, the slave module will detect both
addresses, ‘
0000000
’ and ‘
00100000
’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
18.7
IPMI Support
The control bit, IPMIEN, enables the module to support
the Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
the Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
18.8
General Call Address Support
The general call address can address all devices.
When this address is used, all devices should, in
theory, respond with an Acknowledgement.
When this address is used, all devices should, in
theory, respond with an Acknowledgement.
The general call address is one of eight addresses
reserved for specific purposes by the I
reserved for specific purposes by the I
2
C protocol. It
consists of all ‘
0
’s with R_W =
0
.
The general call address is recognized when the General
Call Enable (GCEN) bit is set (I2CxCON<7> =
Call Enable (GCEN) bit is set (I2CxCON<7> =
1
). When
the interrupt is serviced, the source for the interrupt can
be checked by reading the contents of the I2CxRCV to
determine if the address was device-specific or a general
call address.
be checked by reading the contents of the I2CxRCV to
determine if the address was device-specific or a general
call address.
18.9
Automatic Clock Stretch
In Slave modes, the module can synchronize buffer
reads and write to the master device by clock stretching.
reads and write to the master device by clock stretching.
18.9.1
TRANSMIT CLOCK STRETCHING
Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared,
indicating the buffer is empty.
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock, if the TBF bit is cleared,
indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
performed, irrespective of the STREN bit. The user’s
ISR must set the SCLREL bit before transmission is
allowed to continue. By holding the SCLx line low, the
user has time to service the ISR and load the contents
of the I2CxTRN before the master device can initiate
another transmit sequence.
performed, irrespective of the STREN bit. The user’s
ISR must set the SCLREL bit before transmission is
allowed to continue. By holding the SCLx line low, the
user has time to service the ISR and load the contents
of the I2CxTRN before the master device can initiate
another transmit sequence.
18.9.2
RECEIVE CLOCK STRETCHING
The STREN bit in the I2CxCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCLx pin will be held low at
the end of each data receive sequence.
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCLx pin will be held low at
the end of each data receive sequence.
The user’s ISR must set the SCLREL bit before recep-
tion is allowed to continue. By holding the SCLx line
low, the user has time to service the ISR and read the
contents of the I2CxRCV before the master device can
initiate another receive sequence. This will prevent
buffer overruns from occurring.
tion is allowed to continue. By holding the SCLx line
low, the user has time to service the ISR and read the
contents of the I2CxRCV before the master device can
initiate another receive sequence. This will prevent
buffer overruns from occurring.
18.10 Software Controlled Clock
Stretching (STREN =
1
)
When the STREN bit is ‘
1
’, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching.
clock stretching.
If the STREN bit is ‘
0
’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
SCLREL bit.
0x00
General call address or Start byte
0x01-0x03
Reserved
0x04-0x07
Hs mode Master codes
0x08-0x77
Valid 7-bit addresses
0x78-0x7b
Valid 10-bit addresses
(lower 7 bits)
(lower 7 bits)
0x7c-0x7f
Reserved