Microchip Technology MA330028 数据表
2011-2013 Microchip Technology Inc.
DS70000657H-page 277
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 6
STREN:
SCLx Clock Stretch Enable bit (when operating as I
2
C slave)
Used in conjunction with the SCLREL bit.
1
1
= Enables software or receives clock stretching
0
= Disables software or receives clock stretching
bit 5
ACKDT:
Acknowledge Data bit (when operating as I
2
C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1
1
= Sends NACK during Acknowledge
0
= Sends ACK during Acknowledge
bit 4
ACKEN:
Acknowledge Sequence Enable bit
(when operating as I
2
C master, applicable during master receive)
1
= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware
is clear at the end of the master Acknowledge sequence.
0
= Acknowledge sequence is not in progress
bit 3
RCEN:
Receive Enable bit (when operating as I
2
C master)
1
= Enables Receive mode for I
2
C. Hardware is clear at the end of the eighth bit of the master receive
data byte.
0
= Receive sequence is not in progress
bit 2
PEN:
Stop Condition Enable bit (when operating as I
2
C master)
1
= Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of the master Stop
sequence.
0
= Stop condition is not in progress
bit 1
RSEN:
Repeated Start Condition Enable bit (when operating as I
2
C master)
1
= Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of the
master Repeated Start sequence.
0
= Repeated Start condition is not in progress
bit 0
SEN:
Start Condition Enable bit (when operating as I
2
C master)
1
= Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start
sequence.
0
= Start condition is not in progress
REGISTER 19-1:
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
Note 1:
When performing master operations, ensure that the IPMIEN bit is set to ‘0’.