Microchip Technology AC244044 数据表

PIC16(L)F1825/1829

DS41440C-page 92

 2010-2012 Microchip Technology Inc.

8.6.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as
shown in

Note:

Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.

REGISTER 8-3:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

U-0

R/W-0/0

OSFIE

C2IE

(1)

C1IE

EEIE

BCL1IE

—

CCP2IE

bit 7

bit 0

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt

bit 6

C2IE: Comparator C2 Interrupt Enable bit

(1)

1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt

bit 5

C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt

bit 4

EEIE: EEPROM Write Completion Interrupt Enable bit
1 = Enables the EEPROM write completion interrupt
0 = Disables the EEPROM write completion interrupt

bit 3

BCL1IE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP bus collision interrupt
0 = Disables the MSSP bus collision interrupt

bit 2-1

Unimplemented: Read as ‘0’

bit 0

CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

Note 1:

PIC16(L)F1829 only.