Microchip Technology DM164134 数据表
© 2006 Microchip Technology Inc.
DS41159E-page 395
PIC18FXX8
16-bit Read/Write Mode ............................................ 115
Associated Registers ................................................ 116
Operation .................................................................. 114
Oscillator ........................................................... 113, 115
Overflow Interrupt ............................................. 113, 115
Special Event Trigger (CCP)............................. 115, 126
Special Event Trigger (ECCP) .................................. 133
TMR1H Register ....................................................... 113
TMR1L Register........................................................ 113
TMR3L Register........................................................ 119
Associated Registers ................................................ 116
Operation .................................................................. 114
Oscillator ........................................................... 113, 115
Overflow Interrupt ............................................. 113, 115
Special Event Trigger (CCP)............................. 115, 126
Special Event Trigger (ECCP) .................................. 133
TMR1H Register ....................................................... 113
TMR1L Register........................................................ 113
TMR3L Register........................................................ 119
Associated Registers ................................................ 118
Operation .................................................................. 117
Postscaler.
Operation .................................................................. 117
Postscaler.
Postscaler, Timer2.
See
Prescaler, Timer2.
SSP Clock Shift................................................. 117, 118
TMR2 Register.......................................................... 117
TMR2 to PR2 Match Interrupt ................... 117, 118, 128
TMR2 Register.......................................................... 117
TMR2 to PR2 Match Interrupt ................... 117, 118, 128
Associated Registers ................................................ 121
Operation .................................................................. 120
Oscillator ................................................................... 121
Overflow Interrupt ............................................. 119, 121
Special Event Trigger (CCP)..................................... 121
TMR3H Register ....................................................... 119
Operation .................................................................. 120
Oscillator ................................................................... 121
Overflow Interrupt ............................................. 119, 121
Special Event Trigger (CCP)..................................... 121
TMR3H Register ....................................................... 119
Timing Diagrams
A/D Conversion ......................................................... 359
Acknowledge Sequence ........................................... 176
Baud Rate Generator with
Acknowledge Sequence ........................................... 176
Baud Rate Generator with
CLKO and I/O ........................................................... 344
Clock Synchronization .............................................. 163
Clock/Instruction Cycle ............................................... 41
External Clock........................................................... 343
First Start Bit ............................................................. 171
Full-Bridge PWM Output ........................................... 137
Clock Synchronization .............................................. 163
Clock/Instruction Cycle ............................................... 41
External Clock........................................................... 343
First Start Bit ............................................................. 171
Full-Bridge PWM Output ........................................... 137
I
I
I
I
I
I
I
I
I
Master SSP I
Parallel Slave Port Read .......................................... 108
Parallel Slave Port Write........................................... 107
PWM Direction Change ............................................ 139
PWM Direction Change at Near
Parallel Slave Port Write........................................... 107
PWM Direction Change ............................................ 139
PWM Direction Change at Near
PWM Output ............................................................. 128
Repeated Start Condition ......................................... 172
Reset, Watchdog Timer (WDT),
Repeated Start Condition ......................................... 172
Reset, Watchdog Timer (WDT),
Slave Synchronization .............................................. 149
Slow Rise Time (MCLR Tied to V
Slow Rise Time (MCLR Tied to V
SPI Master Mode...................................................... 148
SPI Master Mode Example (CKE = 0) ...................... 349
SPI Master Mode Example (CKE = 1) ...................... 350
SPI Slave Mode (with CKE = 0)................................ 150
SPI Slave Mode (with CKE = 1)................................ 150
SPI Slave Mode Example (CKE = 0) ........................ 351
SPI Slave Mode Example (CKE = 1) ........................ 352
Stop Condition Receive or
SPI Master Mode Example (CKE = 0) ...................... 349
SPI Master Mode Example (CKE = 1) ...................... 350
SPI Slave Mode (with CKE = 0)................................ 150
SPI Slave Mode (with CKE = 1)................................ 150
SPI Slave Mode Example (CKE = 0) ........................ 351
SPI Slave Mode Example (CKE = 1) ........................ 352
Stop Condition Receive or
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to V
DD
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
)
Time-out Sequence on Power-up
(MCLR Tied to V
DD