Microchip Technology DM164134 数据表
PIC18FXX8
DS41159E-page 80
© 2006 Microchip Technology Inc.
REGISTER 8-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-1
R/W-1
U-0
U-0
R/W-1
U-0
R/W-1
RBPU
INTEDG0 INTEDG1
—
—
TMR0IP
—
RBIP
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1
= All PORTB pull-ups are disabled
0
= PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 4-3
Unimplemented: Read as ‘0’
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
Unimplemented: Read as ‘0’
bit 0
RBIP: RB Port Change Interrupt Priority bit
1
= High priority
0
= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows software polling.
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows software polling.