Microchip Technology DM183037 数据表
PIC18F97J94 FAMILY
DS30575A-page 90
2012 Microchip Technology Inc.
5.2
Power-on Reset (POR)
The PIC18F97J94 family has two types of Power-on
Resets:
• POR
• V
Resets:
• POR
• V
BAT
POR
POR is the legacy PIC18J series Power-on Reset which
monitors core power supply. The second, V
monitors core power supply. The second, V
BAT
POR,
monitors voltage on the V
BAT
pin. These POR circuits
use the same technique to enable and monitor their
respective power source for adequate voltage levels to
ensure proper chip operation. There are two threshold
voltages associated with them. The first voltage is the
device threshold voltage, V
respective power source for adequate voltage levels to
ensure proper chip operation. There are two threshold
voltages associated with them. The first voltage is the
device threshold voltage, V
POR
. The device threshold
voltage is the voltage at which the POR module
becomes operable. The second voltage associated with
a POR event is the POR circuit threshold voltage. Once
the correct threshold voltage is detected, a power-on
event occurs and the POR module hibernates to
minimize current consumption.
A power-on event generates an internal POR pulse
when a V
becomes operable. The second voltage associated with
a POR event is the POR circuit threshold voltage. Once
the correct threshold voltage is detected, a power-on
event occurs and the POR module hibernates to
minimize current consumption.
A power-on event generates an internal POR pulse
when a V
DD
rise is detected. The device supply voltage
characteristics must meet the specified starting voltage,
V
V
POR
, and rise rate requirements, SV
DD
, to generate the
POR pulse. In particular, V
DD
must fall below V
POR
before a new POR is initiated. For more information on
the V
the V
POR
and V
DD
rise rate specifications, refer to
.
5.2.1
POR CIRCUIT
The POR circuit behaves differently than V
BAT
POR
once the POR state becomes active. The internal POR
pulse resets the POR timer and places the device in the
Reset state. The POR also selects the device clock
source identified by the Oscillator Configuration bits.
After the POR pulse is generated, the POR circuit
inserts a small delay, T
pulse resets the POR timer and places the device in the
Reset state. The POR also selects the device clock
source identified by the Oscillator Configuration bits.
After the POR pulse is generated, the POR circuit
inserts a small delay, T
CSD
, to ensure that internal
device bias circuits are stable.
After the expiration of T
CSD
, a delay, T
PWRT
, is always
inserted every time the device resumes operation after
any power-down. During this time, code execution is
disabled. The PWRT is used to extend the duration of
a power-up sequence to permit the on-chip band gap
and regulator to stabilize and to load the Configuration
Word settings. The on-chip regulator is always enabled
and its stabilization time is shorter than other concur-
rently running delays, and does not extend start-up
time.
The power-on event clears the BOR and POR status
bits (RCON<1:0>); it does not change for any other
Reset event. POR is not reset to ‘1’ by any hardware
event. To capture multiple events, the user manually
resets the bit to ‘1’ in software following any Power-on
Reset. Alternatively, the VDDPOR (RCON3<2>) bit can
be used; it is set on a V
any power-down. During this time, code execution is
disabled. The PWRT is used to extend the duration of
a power-up sequence to permit the on-chip band gap
and regulator to stabilize and to load the Configuration
Word settings. The on-chip regulator is always enabled
and its stabilization time is shorter than other concur-
rently running delays, and does not extend start-up
time.
The power-on event clears the BOR and POR status
bits (RCON<1:0>); it does not change for any other
Reset event. POR is not reset to ‘1’ by any hardware
event. To capture multiple events, the user manually
resets the bit to ‘1’ in software following any Power-on
Reset. Alternatively, the VDDPOR (RCON3<2>) bit can
be used; it is set on a V
DD
POR event. It must be
cleared after any Power-on Reset to detect subsequent
V
V
DD
POR events.
After T
PWRT
expires, an additional start-up time for the
system clock (either T
OST
, T
IOBST
and T
RC
, depending
on the source) occurs while the clock source becomes
stable. Internal Reset is then released and the device
is no longer held in Reset (
stable. Internal Reset is then released and the device
is no longer held in Reset (
Once all of the
for more information on
the values of the delay parameters.
Note:
When the device exits the Reset condition
(begins normal operation), the device
operating parameters (voltage, frequency,
temperature, etc.) must be within their
operating ranges; otherwise, the device
will not function correctly. The user must
ensure that the delay between the time
power is first applied, and the time,
INTERNAL RESET, becomes inactive, is
long enough to get all operating
parameters within specification.
(begins normal operation), the device
operating parameters (voltage, frequency,
temperature, etc.) must be within their
operating ranges; otherwise, the device
will not function correctly. The user must
ensure that the delay between the time
power is first applied, and the time,
INTERNAL RESET, becomes inactive, is
long enough to get all operating
parameters within specification.