Microchip Technology MA160014 数据表
PIC18(L)F2X/4XK22
DS41412F-page 150
2010-2012 Microchip Technology Inc.
TABLE 10-13: CONFIGURATION REGISTERS ASSOCIATED WITH PORTD
Pin Name
Function
TRIS
Setting
ANSEL
setting
Pin
Type
Buffer
Type
Description
RD6/P1C/TX2/CK2/
AN26
AN26
RD6
0
0
O
DIG
LATD<6> data output; not affected by analog input.
1
0
I
ST
PORTD<6> data input; disabled when analog input
enabled.
enabled.
P1C
0
0
O
DIG
Enhanced CCP1 PWM output 3.
TX2
1
0
O
DIG
EUSART asynchronous transmit data output.
CK2
1
0
O
DIG
EUSART synchronous serial clock output.
1
0
I
ST
EUSART synchronous serial clock input.
AN26
1
1
I
AN
Analog input 26.
RD7/P1D/RX2/DT2/
AN27
AN27
RD7
0
0
O
DIG
LATD<7> data output; not affected by analog input.
1
0
I
ST
PORTD<7> data input; disabled when analog input
enabled.
enabled.
P1D
0
0
O
DIG
Enhanced CCP1 PWM output 4.
RX2
1
0
I
ST
EUSART asynchronous receive data in.
DT2
1
0
O
DIG
EUSART synchronous serial data output.
1
0
I
ST
EUSART synchronous serial data input.
AN27
1
1
I
AN
Analog input 27.
Legend:
AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
= CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
2
C
TM
= Schmitt Trigger input with I
2
C.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
CCP2MX are set.
TABLE 10-11: PORTD I/O SUMMARY (CONTINUED)
TABLE 10-12: REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSELD
(1)
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
—
WUE
ABDEN
CCP1CON
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
CCP2CON
P2M<1:0>
DC2B<1:0>
CCP2M<3:0>
CCP4CON
—
—
DC4B<1:0>
CCP4M<3:0>
LATD
(1)
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
PORTD
(1)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SLRCON
(1)
—
—
—
SLRE
SLRD
SLRC
SLRB
SLRA
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM<3:0>
TRISD
(1)
TRISD7
TRISD6 TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD.
Note 1:
Available on PIC18(L)F4XK22 devices.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CONFIG3H
MCLRE
—
P2BMX
T3CMX
HFOFST
CCP3MX PBADEN
CCP2MX
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD.