Freescale Semiconductor Student Learning Kit with MC9S08QG8 DEMO9S08QG8E DEMO9S08QG8E 用户手册
产品代码
DEMO9S08QG8E
Freescale Semiconductor
9
Power may be sourced to off-board circuitry through the J1 connector. The current limitation of
the USB bus or the on-board regulator must be considered when attempting to source power
to external circuitry. Excessive current drain may damage the target board, the host PC USB
hub, or the on-board regulator. The figure below details the VX_EN option header
connections.
the USB bus or the on-board regulator must be considered when attempting to source power
to external circuitry. Excessive current drain may damage the target board, the host PC USB
hub, or the on-board regulator. The figure below details the VX_EN option header
connections.
Figure 2. VX_EN Option Header
ON Enable power connection to connector J1
VX_EN
▪
▪ OFF Disable power connection to connector J1
VX_EN
CAUTION: Do not apply power to connector J1 while also sourcing power from either the PWR
connector or the USB-BDM circuit. Damage to the board may result.
NOTE: Do not exceed available current supply from the USB-BDM cable or on-board regulator
when sourcing power through connector J1 to external circuitry.
RESET SWITCH
The RESET switch provides a method to apply an asynchronous reset to the MCU and is
connected directly to the PTA5/RESET* input on the MCU. Pressing the RESET switch forces
the MCU RESET* input low. The MC9S08QG8 MCU applies an internal pull-up on the
RESET* line to prevent spurious resets and allow normal operation.
connected directly to the PTA5/RESET* input on the MCU. Pressing the RESET switch forces
the MCU RESET* input low. The MC9S08QG8 MCU applies an internal pull-up on the
RESET* line to prevent spurious resets and allow normal operation.
LOW VOLTAGE DETECT
The MC9S08QG8 utilizes an internal Low Voltage Detect (LVD) to protect against under-
voltage conditions. The LVD is enabled out of RESET. Consult the MC9S08QG8 Device User
Guide for details on configuring LVD operation.
voltage conditions. The LVD is enabled out of RESET. Consult the MC9S08QG8 Device User
Guide for details on configuring LVD operation.
STOP MODES
The MC9S08QG8 can be configured for three different low power stop modes. If stop1 or
stop2 modes are entered, an external pull-up resistor must be placed between the
PTA5/RESET*/IRQ*/TCLK pin and VDD. This pull-up resistor is not included on the
APS08QG8SLK board. If these modes will be used with this board, a 10K – 50K ohm resistor
can be placed between pins J1-1 and J1-2 to ensure proper operation of the MCU. The
jumper for the VX_EN header must also be in place in this case. Consult the MC9S08QG8
Device User Guide for more details on configuring the low power stop modes.
stop2 modes are entered, an external pull-up resistor must be placed between the
PTA5/RESET*/IRQ*/TCLK pin and VDD. This pull-up resistor is not included on the
APS08QG8SLK board. If these modes will be used with this board, a 10K – 50K ohm resistor
can be placed between pins J1-1 and J1-2 to ensure proper operation of the MCU. The
jumper for the VX_EN header must also be in place in this case. Consult the MC9S08QG8
Device User Guide for more details on configuring the low power stop modes.
TIMING
By default, the APS08QG8SLK uses timing provided from an internal 32 kHz frequency
reference and an internal frequency-locked loop (FLL). The FLL output is trimmable to ± 0.2%
reference and an internal frequency-locked loop (FLL). The FLL output is trimmable to ± 0.2%