Freescale Semiconductor Xtrinsic MAG3110 Magnetometer RD4247MAG3110 RD4247MAG3110 数据表

Sensors

10

Freescale Semiconductor, Inc.

MAG3110 is a small low-power, digital output, 3-axis linear magnetometer packaged in a 10-pin DFN. The device contains a 
magnetic transducer for sensing and an ASIC for control and digital I

2

C communications. 

MAG3110 is factory calibrated for sensitivity and temperature coefficient of sensitivity. All factory calibration coefficients are 
automatically applied by the ASIC before a measurement is taken and the result written to registers 0x01 to 0x06 (

). 

The magnetic offset registers in addresses 0x09 to 0x0E are not a factory calibration offset but allow the user to define a hard-
iron offset which can be automatically subtracted from the magnetic field readings (see 

).

There are two signals associated with the I

2

C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). External pullup 

resistors (connected to VDDIO) are needed for SDA and SCL. When the bus is free, both lines are high. The I

2

C interface is 

compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I

2

C standards.

There are two signals associated with the I

2

C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). The latter is a 

bidirectional line used for sending and receiving the data to/from the interface. External pullup resistors connected to VDDIO are 
required for SDA and SCL. When the bus is free both the lines are high. The I

2

C interface is compliant with fast mode (400 kHz), 

and normal mode (100 kHz) I

2

C standards. Operation at frequencies higher than 400 kHz is possible, but depends on several 

factors including the pullup resistor values, and total bus capacitance (trace + device capacitance).

A transaction on the bus is started with a start condition (ST) signal, which is defined as a HIGH-to-LOW transition on the data 
line while the SCL line is held HIGH. After the ST signal has been transmitted by the master, the bus is considered busy. The 
next byte of data transmitted contains the slave address in the first seven bits, and the eighth bit, the read/write bit, indicates 
whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in 
the system compares the first seven bits after the ST condition with its own address. If they match, the device considers itself 
addressed by the master. The 9th clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge 
(ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it 
remains stable low during the high period of the acknowledge clock period.

The number of bytes per transfer is unlimited. If a receiver can't receive another complete byte of data until it has performed some 
other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the 
receiver is ready for another byte and releases the data line. This delay action is called clock stretching. Not all receiver devices 
support clock stretching. Not all master devices recognize clock stretching. This part supports clock stretching.

STANDBY

I

2

C communication is possible.

Only POR and Digital blocks are enabled, the Analog subsystem is disabled.

ACTIVE

I

2

C communication is possible.

All blocks are enabled (POR, Digital, Analog).

VDDIO

IO voltage 

SCL

I

2

C Serial Clock

SDA

I

2

C Serial Data

INT

Data ready interrupt pin