Freescale Semiconductor Xtrinsic MAG3110 Magnetometer RD4247MAG3110 RD4247MAG3110 信息指南

Sensors

 

2

Freescale Semiconductor

A: I

2

C is rated up to 400 kHz (Fast Mode) communications. Anything above this has not been verified at 

the moment.

A: 7-bit I

2

C address is fixed as 0x0E.

•

Shift in 0b for Write and 1b for Read

•

Write(0x1C) // for I

2

C Address 0x0E

•

Read(0x1D) // for I

2

C Address 0x0E

A: Some alpha versions of silicon had I

2

C addresses of 0x1D and 0x1C. If you requested samples during 

this preproduction period, your device may not have an I

2

C address of 0x0E. You can try communicating 

with MAG3110 using the above-mentioned addresses. We recommend you request the most recent 
samples and obtain the latest documentation through our website since the latest revision silicon contains 
fixes to the alpha errata.

A: I

2

C read operations, whether it is a BURST read or SINGLE read, must be terminated by a NACK (the 

MASTER must leave SDA floating at the end of the last byte read desired) by the MASTER. Failing to do 
so will cause unwanted behavior.

A: No.

A: The DR_STATUS register contains bits for indicating new data on each of the data registers for the three 
axes (ZDR, YDR, XDR) plus ZYXDR bit that is a logical OR of ZDR, YDR and XDR bits. 

The register also contains bits for indicating an overwrite (OW) condition of the data registers for each 
axis (ZOW, YOW, XOW) plus a ZYXOW bit that is a logical OR of ZOW, YOW and XOW bits.

The DR bits can be cleared by reading the MSB of magnetic data register of the particular axis. This will 
also clear the corresponding OW bit.

OUT_X_MSB should be read first so that the data in registers OUT_X_LSB through OUT_Z_LSB is 
updated.

A: By setting the FR bit, the user can make MAG3110 auto-increment the I

2

C address so that the LSB 

locations are skipped during a burst I

2

C read operation.