Freescale Semiconductor StarterTRAK USB for Automotive Safety Applications TRK-USB-MPC5643L TRK-USB-MPC5643L 数据表

Freescale Semiconductor

93

t

lpll

D FMPLL lock time 

6, 7

—

—

—

200

s

t

dc

D Duty cycle of reference

 

—

40

—

60

%

C

JITTER

T CLKOUT period jitter

8,9,10,11

Long-term jitter (avg. over 2 ms 
interval), f

FMPLLOUT

 maximum

–6

—

6

ns



t

PKJIT

T Single period jitter (peak to 

peak)

PHI @ 120 MHz,
Input clock @ 4 MHz

—

—

175

ps

PHI @ 100 MHz,
Input clock @ 4 MHz

—

—

185

ps

PHI @ 80 MHz,
Input clock @ 4 MHz

—

—

200

ps



t

LTJIT

T Long term jitter

PHI @ 16 MHz,
Input clock @ 4 MHz

—

—

±6

ns

f

LCK

D Frequency LOCK range

—

–6

—

6

% f

FMPLLOUT

f

UL

D Frequency un-LOCK range

—

–18

—

18

% f

FMPLLOUT

f

CS

f

DS

D Modulation depth

Center spread

±0.25

—

±2.0

%

f

FMPLLOUT

Down spread

–0.5

—

-8.0

f

MOD

D Modulation frequency

12

—

—

—

100

kHz

1

Considering operation with FMPLL not bypassed.

2

With FM; the value does not include a possible +2% modulation

3

“Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked 
mode.

4

Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside 
the f

LOR

 window.

5

f

VCO

 is the frequency at the output of the VCO; its range is 256–512 MHz.

f

SCM

 is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.

f

SYS

= f

VCO

ODF

6

This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this 
FMPLL, load capacitors should not exceed these limits.

7

This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits 
in the synthesizer control register (SYNCR).

8

This value is determined by the crystal manufacturer and board design.

9

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

SYS

. 

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. 
Noise injected into the FMPLL circuitry via V

DDPLL

 and V

SSPLL

 and variation in crystal oscillator frequency increase the 

C

JITTER

 percentage for a given interval.

10

Proper PC board layout procedures must be followed to achieve specifications.

11

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER

 and 

either f

CS

 or f

DS 

(depending on whether center spread or down spread modulation is enabled).

12

Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.