Freescale Semiconductor Lite5200B: Evaluation Board for the MPC5200B CWMPCEVB5200BE CWMPCEVB5200BE 数据表
产品代码
CWMPCEVB5200BE
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
17
2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt
sources. Take care of interrupt prioritization which may increase the latencies.
Because all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has
to exceed a minimum pulse width of more than one IP_CLK cycle.
to exceed a minimum pulse width of more than one IP_CLK cycle.
NOTES:
1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200B User’s Manual
(MPC5200BUM) for further information.
2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second
interrupt is not recognized at all.
Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt
service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended
to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design
and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.
service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended
to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design
and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.
1.3.6
SDRAM
1.3.6.1
Memory Interface Timing-Standard SDRAM Read Command
Table 17. Minimum Pulse Width for External Interrupts to be Recognized
Name
Min Pulse Width
Max Pulse Width
Reference Clock
SpecID
All external interrupts (IRQs, GPIOs)
> 1 clock cycle
—
IP_CLK
A4.22
Table 18. Standard SDRAM Memory Read Timing
Sym
Description
Min
Max
Units
SpecID
t
mem_clk
MEM_CLK period
7.5
—
ns
A5.1
t
valid
Control Signals, Address and MBA Valid after
rising edge of MEM_CLK
—
t
mem_clk
× 0.5 + 0.4
ns
A5.2
t
hold
Control Signals, Address and MBA Hold after
rising edge of MEM_CLK
t
mem_clk
× 0.5
—
ns
A5.3
DM
valid
DQM valid after rising edge of MEM_CLK
—
t
mem_clk
× 0.25 + 0.4
ns
A5.4
DM
hold
DQM hold after rising edge of MEM_CLK
t
mem_clk
× 0.25 – 0.7
—
ns
A5.5
data
setup
MDQ setup to rising edge of MEM_CLK
—
0.3
ns
A5.6
data
hold
MDQ hold after rising edge of MEM_CLK
0.2
—
ns
A5.7