Freescale Semiconductor DEMO9S08DZ60 Demo Board DEMO9S08DZ60 DEMO9S08DZ60 数据表
产品代码
DEMO9S08DZ60
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
MC9S08DZ60 Series Data Sheet, Rev. 4
182
Freescale Semiconductor
If the MODE bits are changed, any data in ADCRH becomes invalid.
10.3.4
Data Result Low Register (ADCRL)
ADCRL contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an
8-bit conversion. This register is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. When a compare event does occur, the value is
the addition of the conversion result and the two’s complement of the compare value. In 12-bit and 10-bit
mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, the
intermediate conversion results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE
bits are changed, any data in ADCRL becomes invalid.
8-bit conversion. This register is updated each time a conversion completes except when automatic
compare is enabled and the compare condition is not met. When a compare event does occur, the value is
the addition of the conversion result and the two’s complement of the compare value. In 12-bit and 10-bit
mode, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed, the
intermediate conversion results are lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE
bits are changed, any data in ADCRL becomes invalid.
10.3.5
Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. When the
compare function is enabled, these bits are compared to the upper four bits of the result following a
conversion in 12-bit mode.
compare function is enabled, these bits are compared to the upper four bits of the result following a
conversion in 12-bit mode.
7
6
5
4
3
2
1
0
R
0
0
0
0
ADR11
ADR10
ADR9
ADR8
W
Reset:
0
0
0
0
0
0
0
0
Figure 10-5. Data Result High Register (ADCRH)
7
6
5
4
3
2
1
0
R
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
W
Reset:
0
0
0
0
0
0
0
0
Figure 10-6. Data Result Low Register (ADCRL)
7
6
5
4
3
2
1
0
R
0
0
0
0
ADCV11
ADCV10
ADCV9
ADCV8
W
Reset:
0
0
0
0
0
0
0
0
Figure 10-7. Compare Value High Register (ADCCVH)