Freescale Semiconductor DEMO9S08DZ60 Demo Board DEMO9S08DZ60 DEMO9S08DZ60 数据表
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DEMO9S08DZ60
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ60 Series Data Sheet, Rev. 4
238
Freescale Semiconductor
Read: Anytime
Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored
Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored
12.3.13 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
INITAK = 1)
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
functionality.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
BOHOLD
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-16. MSCAN Miscellaneous Register (CANMISC)
Table 12-19. CANMISC Register Field Descriptions
Field
Description
0
BOHOLD
Bus-off State Hold Until User Request — If BORM is set in
this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the
recovery from bus-off. Refer to
,” for details.
0 Module is not bus-off or recovery has been requested by user in bus-off state
1 Module is bus-off and holds this state until user request
1 Module is bus-off and holds this state until user request
7
6
5
4
3
2
1
0
R
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-17. MSCAN Receive Error Counter (CANRXERR)