Freescale Semiconductor DEMO9S08DZ60 Demo Board DEMO9S08DZ60 DEMO9S08DZ60 数据表

382

Freescale Semiconductor

18

T

RMS frequency variation of a single clock cycle

measured 625 ns after reference edge.

6

f

pll_cycjit_625ns

—

—

%f

pll

19

T

Maximum frequency variation averaged over
625 ns window.

f

pll_maxjit_625ns

—

0.113

—

%f

pll

20

D Lock entry frequency tolerance

7

D

lock

±

1.49

—

±

2.98

%

21

D Lock exit frequency tolerance

8

D

unl

±

4.47

—

±

5.97

%

22

D Lock time - FLL

t

fll_lock

—

—

t

fll_acquire+

1075(1/

f

int_t)

s

23

D Lock time - PLL

t

pll_lock

—

—

t

pll_acquire+

1075(1/

f

pll_ref)

s

24

D

Loss of external clock minimum frequency -
RANGE = 0

f

loc_low

(3/5) x f

int

—

—

kHz

25

D

Loss of external clock minimum frequency -
RANGE = 1

f

loc_high

(16/5) x f

int

—

—

kHz

1

TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).

2

This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the
reference, this specification assumes it is already running.

3

This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it
is already running.

4

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

BUS

.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V

DD

and V

SS

and variation in crystal oscillator frequency increase the C

Jitter

percentage for

a given interval. Jitter measurements are based upon a 40MHz MCGOUT clock frequency.

5

In some specifications, this value is described as “long term accuracy of PLL output clock (averaged over 2 ms)” with symbol
“f

pll_jitter_2ms

.” The parameter is unchanged, but the description has been changed for clarification purposes.

6

In some specifications, this value is described as “Jitter of PLL output clock measured over 625 ns” with symbol
“f

pll_jitter_625ns

.” The parameter is unchanged, but the description has been changed for clarification purposes.

7

Below D

lock

 minimum, the MCG is guaranteed to enter lock. Above D

lock

 maximum, the MCG will not enter lock. But if the

MCG is already in lock, then the MCG may stay in lock.

8

Below D

unl

 minimum, the MCG will not exit lock if already in lock. Above D

unl

 maximum, the MCG is guaranteed to exit lock.

°