Freescale Semiconductor DEMO9S08DZ60 Demo Board DEMO9S08DZ60 DEMO9S08DZ60 数据表
产品代码
DEMO9S08DZ60
Appendix B Timer Pulse-Width Modulator (TPMV2)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
395
B.2.2
Timer Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPMxSC).
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPMxSC).
Reset clears the TPM counter registers.
Table B-2. TPM Clock Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
0:0
No clock selected (TPMx disabled)
0:1
Bus rate clock (BUSCLK)
1:0
Fixed system clock (XCLK)
1:1
External source (TPMxCLK)
1,2
1
The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
frequency.
2
If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.
the corresponding ELSnB:ELSnA control bits should be set to 0:0 so channel n does not try
to use the same pin for a conflicting function.
Table B-3. Prescale Divisor Selection
PS2:PS1:PS0
TPM Clock Source Divided-By
0:0:0
1
0:0:1
2
0:1:0
4
0:1:1
8
1:0:0
16
1:0:1
32
1:1:0
64
1:1:1
128
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Any write to TPMxCNTH clears the 16-bit counter.
Reset
0
0
0
0
0
0
0
0
Figure B-3. Timer Counter Register High (TPMxCNTH)