Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
133
2.3.72
PIM Reserved Registers
2.3.73
Port T Interrupt Enable Register (PIET)
Read: Anytime.
Table 2-57. WOMR Register Field Descriptions
Field
Description
7-0
WOMR
Port R wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
Address 0x0287
Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
Write: Unimplemented
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-69. PIM Reserved Registers
Address 0x0288
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
PIET7
PIET6
PIET5
PIET4
PIET3
PIET2
PIET1
PIET0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-70. Port TInterrupt Enable Register (PIET)
Table 2-58. PIET Register Field Descriptions
Field
Description
7-0
PIET
Port T interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port T.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port T.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).