Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Memory Mapping Control (S12XMMCV4)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
169
3.3.2.7
Data FLASH Page Index Register (EPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 1KB blocks into the Data FLASH page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see
accessing up to 256KB of Data FLASH (in the Global map) within the 64KB Local map. The Data FLASH
page index register is effectively used to construct paged Data FLASH addresses in the Local map format.
page index register is effectively used to construct paged Data FLASH addresses in the Local map format.
Figure 3-16. EPAGE Address Mapping
Address: 0x0017
7
6
5
4
3
2
1
0
R
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
W
Reset
1
1
1
1
1
1
1
0
Figure 3-15. Data FLASH Page Index Register (EPAGE)
Table 3-9. EPAGE Field Descriptions
Field
Description
7–0
EP[7:0]
Data FLASH Page Index Bits 7–0 — These page index bits are used to select which of the 256 Data FLASH
array pages is to be accessed in the Data FLASH Page Window.
array pages is to be accessed in the Data FLASH Page Window.
Bit16
Bit0
Bit9
Address [9:0]
EPAGE Register [7:0]
Global Address [22:0]
Bit10
Bit17
0
0
1
0
0
Address: CPU Local Address
or BDM Local Address