Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

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After system reset, software should:

•

Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF10–0xFFF9).

•

Initialize the interrupt processing level configuration data registers (INT_CFADDR,
INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request
target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.

•

If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and
configure the XGATE module (please refer the XGATE Block Guide for details).

•

Enable I maskable interrupts by clearing the I bit in the CCR.

•

Enable the X maskable interrupt by clearing the X bit in the CCR (if required).

The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I bit maskable interrupt requests handled by the CPU.

•

I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to

 for an example using up to three nested interrupt requests).

I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can
interrupt the current ISR.

An ISR of an interruptible I bit maskable interrupt request could basically look like this:

•

Service interrupt, e.g., clear interrupt flags, copy data, etc.

•

Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with
higher priority)

•

Process data

•

Return from interrupt by executing the instruction RTI