Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

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Freescale Semiconductor

The comparators monitor the bus activity of the CPU12X. When a match occurs the control logic can
trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered and/or
a breakpoint can be generated.

Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered   by writing to the TRIG control bit.

The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.

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Four comparators (A, B, C, and D)
— Comparators A and C compare the full address bus and full 16-bit data bus
— Comparators A and C feature a data bus mask register
— Comparators B and D compare the full address bus only
— Each comparator can be configured to monitor CPU12X buses
— Each comparator features selection of read or write access cycles
— Comparators B and D allow selection of byte or word access cycles
— Comparisons can be used as triggers for the state sequencer

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Three comparator modes
— Simple address/data comparator match mode
— Inside address range mode, Addmin

≤ Address ≤ Addmax

— Outside address range match mode, Address

< Addmin or Address > Addmax

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Two types of triggers
— Tagged — This triggers just before a specific instruction begins execution
— Force — This triggers on the first instruction boundary after a match occurs.

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The following types of breakpoints
— CPU12X breakpoint entering BDM on breakpoint (BDM)
— CPU12X breakpoint executing SWI on breakpoint (SWI)

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TRIG Immediate software trigger independent of comparators

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Four trace modes

Data Line

64-bit data entity

CPU

CPU12X module

Tag

Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the
execution stage a tag hit occurs.