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DEMO9S12XHY256
S12X Debug (S12XDBGV3) Module
MC9S12XHY-Family Reference Manual, Rev. 1.04
232
Freescale Semiconductor
6.3.2.3
Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
Bits 5:0 anytime the module is disarmed.
WARNING
DBGTCR[7] is reserved. Setting this bit maps the tracing to an unimplemented bus, thus
preventing proper operation.
Table 6-7. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0]
Current State
000
State0 (disarmed)
001
State1
010
State2
011
State3
100
Final State
101,110,111
Reserved
Address: 0x0022
7
6
5
4
3
2
1
0
R
reserved
TSOURCE
TRANGE
TRCMOD
TALIGN
W
Reset
0
0
0
0
0
0
0
0
Figure 6-5. Debug Trace Control Register (DBGTCR)
Table 6-8. DBGTCR Field Descriptions
Field
Description
6
TSOURCE
Trace Source Control Bits — The TSOURCE enables the tracing session. If the MCU system is secured, this
bit cannot be set and tracing is inhibited.
0 No tracing selected
1 Tracing selected
bit cannot be set and tracing is inhibited.
0 No tracing selected
1 Tracing selected
5–4
TRANGE
Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when
tracing from the CPU12X in Detail Mode. To use a comparator for range filtering, the corresponding COMPE
bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state
sequence triggers. See
tracing from the CPU12X in Detail Mode. To use a comparator for range filtering, the corresponding COMPE
bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state
sequence triggers. See
3–2
TRCMOD
Trace Mode Bits — See
for detailed Trace Mode descriptions. In Normal Mode, change of flow
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
.
1–0
TALIGN
Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a
tracing session. See
tracing session. See