Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

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DEMO9S12XHY256
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S12X Debug (S12XDBGV3) Module
MC9S12XHY-Family Reference Manual, Rev. 1.04
242
Freescale Semiconductor
shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
6.3.2.8.2
Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See
 for visible register encoding.
Write: If DBG not armed. See
 for visible register encoding.
0
COMPE
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
Table 6-28. Read or Write Comparison Logic Table
RWE Bit
RW Bit
RW Signal
Comment
0
x
0
RW not used in comparison
0
x
1
RW not used in comparison
1
0
0
Write
1
0
1
No match
1
1
0
No match
1
1
1
Read
Address: 0x0029
7
6
5
4
3
2
1
0
R
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-15. Debug Comparator Address High Register (DBGXAH)
Table 6-29. DBGXAH Field Descriptions
Field
Description
6–0
Bit[22:16]
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. .
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Table 6-27. DBGXCTL Field Descriptions (continued)
Field
Description