Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
S12XE Clocks and Reset Generator (S12XECRGV2)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
263
Figure 7-1. Block diagram of S12XECRG
7.2
Signal Description
This section lists and describes the signals that connect off chip.
7.2.1
V
DDPLL
, V
SSPLL
These pins provides operating voltage (V
DDPLL
) and ground (V
SSPLL
) for the IPLL circuitry. This allows
the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required V
DDPLL
and V
SSPLL
must be connected to properly.
7.2.2
RESET
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
ICRG
Registers
COP
RESET
RTI
IPLL
V
DDPLL
V
SSPLL
EXTAL
XTAL
Bus Clock
System Reset
Oscillator Clock
PLLCLK
OSCCLK
Core Clock
CM Fail
XCLKS
Power on Reset
Low Voltage Reset
COP Timeout
Real Time Interrupt
PLL Lock Interrupt
Self Clock Mode
Interrupt
S12X_MMC
Illegal Address Reset
Reset
Generator
Clock Quality
Checker
Clock and Reset Control
Voltage
Regulator
Clock
Monitor
Oscillator
LCD Clock