Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
345
11.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
11.3.2.1
MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
0x000F
CANTXERR
R
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
W
0x0010–0x0013
CANIDAR0–3
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
0x0014–0x0017
CANIDMRx
R
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
W
0x0018–0x001B
CANIDAR4–7
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
0x001C–0x001F
CANIDMR4–7
R
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
W
0x0020–0x002F
CANRXFG
R
See
W
0x0030–0x003F
CANTXFG
R
See
W
Module Base + 0x0000
Access: User read/write
(1)
7
6
5
4
3
2
1
0
R
RXFRM
RXACT
CSWAI
SYNCH
TIME
WUPE
SLPRQ
INITRQ
W
Reset:
0
0
0
0
0
0
0
1
= Unimplemented
Figure 11-4. MSCAN Control Register 0 (CANCTL0)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 11-3. MSCAN Register Summary (continued)