Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Inter-Integrated Circuit (IICV3) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.04
412
Freescale Semiconductor
12.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
12.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it.If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
the master has driven SCL low the slave can drive SCL low for the required period and then release it.If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
12.4.1.10 Ten-bit Address
A ten-bit address is indicated if the first 5 bits of the first address byte are 0x11110. The following rules
apply to the first address byte.
apply to the first address byte.
Figure 12-13.
Definition of bits in the first byte
.
The address type is identified by ADTYPE. When ADTYPE is 0, 7-bit address is applied. Reversely, the
address is 10-bit address.Generally, there are two cases of 10-bit address.See the
address is 10-bit address.Generally, there are two cases of 10-bit address.See the
.
Figure 12-14. A master-transmitter addresses a slave-receiver with a 10-bit address
Figure 12-15. A master-receiver addresses a slave-transmitter with a 10-bit address.
In the
, the first two bytes are the similar to
. After the repeated START(Sr),the
first slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter.
SLAVE
ADDRESS
R/W BIT
DESCRIPTION
0000000
0
General call address
0000010
x
Reserved for different bus
format
0000011
x
Reserved for future purposes
11111XX
x
Reserved for future purposes
11110XX
x
10-bit slave addressing
S
Slave Add1st 7bits
11110+ADR10+ADR9
R/W
0
A1
Slave Add 2nd byte
ADR[8:1]
A2
Data
A3
S
Slave Add1st 7bits
11110+ADR10+ADR9
R/W
0
A1
Slave Add 2nd byte
ADR[8:1]
A2
Sr
Slave Add 1st 7bits
11110+ADR10+ADR9
R/W
1
A3
Data
A4