Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

产品代码
DEMO9S12XHY256
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页码 924
Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
49
serial peripheral interface (SPI). It can be configured as the serial clock pin SCL of IIC module. It can be
configured as PWM channel 4.
1.7.4
Power Supply Pins
MC9S12XHY-Family power and ground pins are described below. Because fast signal transitions place
high, short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible.
NOTE
All V
SS
 pins must be connected together in the application.
1.7.4.1
VDDX[2:1] / VSSX[2:1] — Power and Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded. All V
DDX
pins are connected together internally. All V
SSX
pins are connected together internally.
1.7.4.2
VDDR — Power Pin for Internal Voltage Regulator
Power supply input to the internal voltage regulator.
1.7.4.3
VDD / VSS2 / VSS3 — Core power Pins
The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current
path is through the VSS2 and VSS3 pin. No static external loading of these pins is permitted.
1.7.4.4
VDDF / VSS1 — NVM Power Pins
The voltage supply of nominally 2.8 V is derived from the internal voltage regulator. The return current
path is through the VSS1 pin. No static external loading of these pins is permitted.
1.7.4.5
VDDA / VSSA — Power Supply Pins for ATD and Voltage Regulator
These are the power supply and ground input pins for the analog-to-digital converters and the voltage
regulator.
1.7.4.6
VDDPLL / VSSPLL — Power Supply Pins for PLL
This pin provides operating voltage and ground for the oscillator and the phased-locked loop. The voltage
supply of nominally 1.8V is derived from the internal voltage regulator. This allows the supply voltage to
the oscillator and PLL to be bypassed independently. This voltage is generated by the internal voltage
regulator. No static external loading of these pins is permitted