Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Electrical Characteristics
MC9S12XHY-Family Reference Manual, Rev. 1.04
728
Freescale Semiconductor
shows the configuration of the peripherals for maximum run current
A.1.10.3
Stop Current Conditions
Unbonded ports must be correctly initialized to prevent current consumption due to floating inputs. Typical
Stop current is measured with V
Stop current is measured with V
DD35
=5V, maximum Stop current is measured with V
DD35
=5.5V. Pseudo
Stop currents are measured with the oscillator configured for 4 MHz LCP mode. Production test
parameters are tested with a 4 MHz square wave oscillator.
parameters are tested with a 4 MHz square wave oscillator.
A.1.10.4
Measurement Results
Table A-8. Module Configurations for Maximum Run Supply (VDDR+VDDA) Current
V
DD35
=5.5V
Peripheral
Configuration
S12XCPU
420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)
COP & RTI
enabled. COP running at the rate 224, RTI control register(RTICTL) set to $7F
PLL
enabled and configured to supply the part with the maximum specified bus frequency (80 MHz).
DBG
the module is enabled and the comparators are configured to trigger in outside range.The range
covers all the code executed by the core,the tracing is disabled..
covers all the code executed by the core,the tracing is disabled..
CAN0,CAN1
Configured to loop-back mode using a bit rate of 1 Mbit/s
SPI
Configured to master mode, continuously transmit data (0x55 or 0xAA) at 1Mbit/s
SCI0,SCI1
Configured into loop mode, with the break detection and collision detection features enabled,
continuously transmit data (0x55) at speed of 57600 baud
continuously transmit data (0x55) at speed of 57600 baud
PWM
Configured to toggle its pins at the rate of 40 kHz
operate in master mode and continuously transimit data(0x55 or 0xAA) at 100Kbits/s
LCD
configured to 976Hz frame frequency, 1/4 Duty, 1/3 Bias with all FP/BP enabled and all
segment on
segment on
MC
configured to full H-bridge mode MCPER=0x3FF, 1/2fbus motor controller timer counter
clock, MCDC=0x20
clock, MCDC=0x20
SSD
disabled
TIM0,TIM1
The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.
counter enabled.
ATD
The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.
frequency and to continuously convert voltages on all input channels in sequence.
Overhead
VREG supplying 1.8V from a 5V input voltage, PLL on