Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

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Freescale Semiconductor

is recommended to configure PortAD pins as outputs only for low frequency, low load outputs. The impact
on ATD accuracy is load dependent and not specified. The values specified are valid under condition that
no PortAD output drivers switch during conversion.

Due to the input pin leakage current as specified in

and

in conjunction with the source

resistance there will be a voltage drop from the signal source to the ATD input. The maximum source
resistance R

S

specifies results in an error (10-bit resolution) of less than 1/2 LSB (2.5 mV) at the maximum

leakage current. If device or operating conditions are less than worst case or leakage-induced error is
acceptable, larger values of source resistance of up to 10Kohm are allowed.

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage

≤ 1LSB (10-bit resilution), then the external filter capacitor, C

f

≥ 1024 * (C

INS

–C

INN

).

There are two cases to consider.

1. A current is injected into the channel being converted. The channel being stressed has conversion

values of $3FF (in 10-bit mode) for analog inputs greater than V

RH

and $000 for values less than

V

RL

 unless the current is higher than specified as disruptive condition.

2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this

current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.

The additional input voltage error on the converted channel can be calculated as:

V

ERR

 = K * R

S

 * I

INJ

with I

INJ

being the sum of the currents injected into the two pins adjacent to the converted channel.