Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册

产品代码
DEMO9S12XHY256
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页码 924
PCB Layout Guidelines
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
765
Appendix C
PCB Layout Guidelines
C.1
General
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins .
Central point of the ground star should be the VSS3 pin.
Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
VSSPLL must be directly connected to VSS3.
Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for
C12,C11, and Q1 as small as possible.
Do not place other signals or supplies underneath area occupied by C12,C11, and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
Example layouts are illustrated on the following pages.
Table C-1. Recommended Decoupling Capacitor Choice
Component
Purpose
Type
Value
C1
V
DDX1
 filter capacitor
X7R/tantalum
>=100 nF
C2
V
DDM1
 filter capacitor
X7R/tantalum
>=47 uF
C3
V
DDM2
 filter capacitor
X7R/tantalum
>=47 uF
C4
V
DDPLL
 filter capacitor
Ceramic X7R
220 nF
C5
V
LCD
 filter capacitor
Ceramic X7R
>=100 nF
C6
V
DDX2
 filter capacitor
X7R/tantalum
>=100 nF
C7
V
DDA
filter capacitor
Ceramic X7R
>=100 nF
C8
V
DDR
 filter capacitor
X7R/tantalum
>=100 nF
C9
V
DD
filter capacitor
Ceramic X7R
220 nF
C10
V
DDF
filter capacitor
Ceramic X7R
220 nF
C11
OSC load capacitor
From crystal manufacturer
C12
OSC load capacitor
Q1
Quartz