Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 用户手册
产品代码
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
107
2.3.32
Port M Input Register (PTIM)
1
PTM
Port M general purpose input/output data—Data Register, SCI1 TXD, PWM channel5,TIM0 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI1 takes precedence over the TIM0 output,PWM5 and general purpose I/O function if enabled
• The TIM0 output function takes precedence over the PWM5 and general purpose I/O function if the related
• The TIM0 output function takes precedence over the PWM5 and general purpose I/O function if the related
channel is enabled.
3
• The PWM5 takes precedence over the general purpose I/O function if enabled
0
PTM
Port M general purpose input/output data—Data Register, SCI1 RXD, PWM channel4,TIM0 output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI1 takes precedence over the TIM0 output,PWM4 and general purpose I/O function if enabled
• The TIM0 output function takes precedence over the PWM4 and general purpose I/O function if the related
• The TIM0 output function takes precedence over the PWM4 and general purpose I/O function if the related
channel is enabled.
4
• The PWM4 takes precedence over the general purpose I/O function if enabled
1
In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0
2
In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0
3
In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0
4
In order TIM input capture to be function correctly, the corresponding DDRT bit should be set to 0
Address 0x0251
Access: User read
1
1
Read: Anytime
Write:Never, writes to this register have no effect.
Write:Never, writes to this register have no effect.
7
6
5
4
3
2
1
0
R
0
0
0
0
PTIM3
PTIM2
PTIM1
PTIM0
W
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-29. Port M Input Register (PTIM)
Table 2-24. Port M Data Register (PTM)
Table 2-25. PTM Register Field Descriptions (continued)
Field
Description