Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 数据表

Freescale Semiconductor

759

1

.

Read: Anytime

Write: Anytime

7:0

OC7M[7:0]

Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,
the output compare action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on

a channel 7 event, even if the corresponding pin is setup for output compare.

1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a

channel 7 event.

Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to

be transferred from the output compare 7 data register to the timer port.

Module Base + 0x0003

7

6

5

4

3

2

1

0

R

OC7D7

OC7D6

OC7D5

OC7D4

OC7D3

OC7D2

OC7D1

OC7D0

W

Reset

0

0

0

0

0

0

0

0

7:0

OC7D[7:0]

Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.

Module Base + 0x0004

15

14

13

12

11

10

9

9

R

TCNT15

TCNT14

TCNT13

TCNT12

TCNT11

TCNT10

TCNT9

TCNT8

W

Reset

0

0

0

0

0

0

0

0