Intel 2.80 GHz BX80546KG2800EA 数据表
产品代码
BX80546KG2800EA
Intel® Xeon™ Processor with 800 MHz System Bus
10
Datasheet
Intel® Xeon™ processor with 800 MHz system bus-based platforms implement independent
power planes for each system bus agent. As a result, the processor core voltage (V
power planes for each system bus agent. As a result, the processor core voltage (V
CC
) and system
bus termination voltage (V
TT
) must connect to separate supplies. The processor core voltage uses
power delivery guidelines denoted by VRM 10.0 or VRM 10.1 and the associated load line (see
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design
Guidelines or Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
10.1 Design Guidelines) for further details.
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design
Guidelines or Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
10.1 Design Guidelines) for further details.
The Intel® Xeon™ processor with 800 MHz system bus uses a scalable system bus protocol
referred to as the “system bus” in this document. The system bus uses a split-transaction, deferred
reply protocol. The system bus uses Source-Synchronous Transfer (SST) of address and data to
improve performance. The processor transfers data four times per bus clock (4X data transfer rate,
as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per
bus clock and is referred to as a ‘double-clocked’ or the 2X address bus. In addition, the Request
Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide
a data bus bandwidth of up to 6.4 GBytes/second (6400 MBytes/second). Finally, the system bus is
also used to deliver interrupts.
referred to as the “system bus” in this document. The system bus uses a split-transaction, deferred
reply protocol. The system bus uses Source-Synchronous Transfer (SST) of address and data to
improve performance. The processor transfers data four times per bus clock (4X data transfer rate,
as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per
bus clock and is referred to as a ‘double-clocked’ or the 2X address bus. In addition, the Request
Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide
a data bus bandwidth of up to 6.4 GBytes/second (6400 MBytes/second). Finally, the system bus is
also used to deliver interrupts.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front side bus” or “System bus” refers to the interface between the processor, system core logic
(a.k.a. the chipset components), and other bus agents. The system bus is a multiprocessing interface
to processors, memory, and I/O. For this document, “front side bus” or “system bus” are used as
generic terms for the “Intel® Xeon™ processor with 800 MHz system bus”.
(a.k.a. the chipset components), and other bus agents. The system bus is a multiprocessing interface
to processors, memory, and I/O. For this document, “front side bus” or “system bus” are used as
generic terms for the “Intel® Xeon™ processor with 800 MHz system bus”.
Commonly used terms are explained here for clarification:
•
Intel® Xeon™ Processor with 800 MHz System Bus — Intel 32-bit microprocessor
intended for dual processor servers and workstations. The Intel® Xeon™ processor with
800 MHz system bus is based on Intel’s 90 nanometer process and will include core frequency
improvements, a large cache array, microarchitectural improvements and additional
instructions. The Intel® Xeon™ processor with 800 MHz system bus will use the mPGA604
socket. For this document, “processor” is used as the generic term for the “Intel® Xeon™
processor with 800 MHz system bus.”
intended for dual processor servers and workstations. The Intel® Xeon™ processor with
800 MHz system bus is based on Intel’s 90 nanometer process and will include core frequency
improvements, a large cache array, microarchitectural improvements and additional
instructions. The Intel® Xeon™ processor with 800 MHz system bus will use the mPGA604
socket. For this document, “processor” is used as the generic term for the “Intel® Xeon™
processor with 800 MHz system bus.”
•
Central Agent — The central agent is the host bridge to the processor and is typically known
as the chipset.
as the chipset.
Table 1.
Features of the Intel® Xeon™ Processor with 800 MHz System Bus
No. of Supported
Symmetric
Agents
L2 Advanced
Transfer
Cache
Front Side Bus
Frequency
Package
Intel® Xeon™ processor with
800 MHz system bus
1 – 2
1 MB
800 MHz
604-pin
FC-mPGA4