Analog Devices AD9609 Evaluation Board AD9609-40EBZ AD9609-40EBZ 数据表
产品代码
AD9609-40EBZ
AD9609
Rev. 0 | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
INDICATOR
1
CLK+
2
CLK–
3
AVDD
4
CSB
5
SCLK/DFS
6
SDIO/PDWN
7
NC
8
NC
24 AVDD
23 MODE/OR
22 DCO
21 D9 (MSB)
20 D8
19 D7
18 D6
17 D5
23 MODE/OR
22 DCO
21 D9 (MSB)
20 D8
19 D7
18 D6
17 D5
9
N
C
1
0
N
C
1
1
(L
S
B
)
D
0
1
2
D
1
1
3
D
R
V
D
D
1
4
D
2
1
5
D
3
1
6
D
4
3
2
A
V
D
D
3
1
V
IN
+
3
0
V
IN
–
2
9
A
V
D
D
2
8
R
B
IA
S
2
7
V
C
M
2
6
S
E
N
S
E
2
5
V
R
E
F
TOP VIEW
(Not to Scale)
AD9609
08
54
1-
0
03
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE SOLDERED TO
THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION,
NOISE, AND MECHANICAL STRENGTH BENEFITS.
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE SOLDERED TO
THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION,
NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0 (Exposed Pad)
AGND
The exposed paddle is the only ground connection. It must be soldered to the analog ground of the
PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
1, 2
CLK+, CLK−
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32
AVDD
1.8 V Supply Pin for ADC Core Domain.
4
CSB
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
5 SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6 SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 15 for details.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 15 for details.
7 to 10
NC
Do not connect.
11 to 12, 14 to 21
D0 (LSB) to
D9 (MSB)
D9 (MSB)
ADC Digital Outputs.
13
DRVDD
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22
DCO
Data Clock Digital Output.
23 MODE/OR
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
25
VREF
1.0 V Voltage Reference Input/Output. See Table 10.
26
SENSE
Reference Mode Selection. See Table 10.
27
VCM
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28
RBIAS
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31
VIN−, VIN+
ADC Analog Inputs.