Analog Devices AD9609 Evaluation Board AD9609-40EBZ AD9609-40EBZ 数据表
产品代码
AD9609-40EBZ
AD9609
Rev. 0 | Page 20 of 32
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9609 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 45) and require no external bias.
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 45) and require no external bias.
0.9V
AVDD
2pF
2pF
CLK–
CLK+
08
54
1-
0
16
Figure 45. Equivalent Clock Input Circuit
Clock Input Options
The AD9609 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of great concern, as described in the Jitter Considerations section.
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of great concern, as described in the Jitter Considerations section.
Figure 46 and Figure 47 show two preferred methods for clock-
ing the AD9609 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
ing the AD9609 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/
balun secondary limit clock excursions into the AD9609 to
approximately 0.8 V p-p differential.
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/
balun secondary limit clock excursions into the AD9609 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9609 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
from feeding through to other portions of the AD9609 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
Ω
100
Ω
CLK–
CLK+
ADC
Mini-Circuits
®
ADT1-1WT, 1:1 Z
XFMR
08
54
1-
0
17
Figure 46. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1µF
0.1µF
1nF
CLOCK
INPUT
1nF
50
Ω
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
08
54
1-
01
8
Figure 47. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 48. The
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 48. The
/
/
excellent jitter performance.
100
Ω
0.1µF
0.1µF
0.1µF
0.1µF
240
Ω
240
Ω
50k
Ω
50k
Ω
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
0
854
1-
01
9
Figure 48. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 49. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
sample clock input pins, as shown in Figure 49. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
100
Ω
0.1µF
0.1µF
0.1µF
0.1µF
50k
Ω
50k
Ω
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
0
854
1-
020
Figure 49. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 50).
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 50).
OPTIONAL
100
Ω
0.1µF
0.1µF
0.1µF
50
Ω
1
1
50
Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
V
CC
1k
Ω
1k
Ω
CLOCK
INPUT
AD951x
CMOS DRIVER
08
54
1-
02
1
Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9609 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the inter-
nal duty cycle stabilizer (DCS) when using divide ratios other
than 1, 2, or 4.
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the inter-
nal duty cycle stabilizer (DCS) when using divide ratios other
than 1, 2, or 4.