Analog Devices AD9609 Evaluation Board AD9609-40EBZ AD9609-40EBZ 数据表
产品代码
AD9609-40EBZ
AD9609
Rev. 0 | Page 7 of 32
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter Temp
AD9609-20/AD9609-40 AD9609-65
AD9609-80
Unit
Min Typ
Max Min Typ Max Min Typ Max
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
625
625
625
MHz
Conversion Rate
Full
3
20/40
3 65
3
80
MSPS
CLK Period—Divide-by-1 Mode (t
CLK
) Full
50/25
15.38
12.5
ns
CLK Pulse Width High (t
CH
)
25.0/12.5
7.69
6.25
ns
Aperture Delay (t
A
)
Full
1.0
1.0
1.0
ns
Aperture Uncertainty (Jitter, t
J
) Full
0.1
0.1
0.1
ps
rms
DATA OUTPUT PARAMETERS
Data Propagation Delay (t
PD
)
Full
3
3
3
ns
DCO Propagation Delay (t
DCO
) Full
3
3
3
ns
DCO to Data Skew (t
SKEW
) Full
0.1
0.1
0.1
ns
Pipeline Delay (Latency)
Full
8
8
8
Cycles
Wake-Up Time
Full
350
350
350
μs
Standby
Full
600/400
300
260
ns
OUT-OF-RANGE
RECOVERY
TIME
Full
2
2 2 Cycles
1
Conversion rate is the clock rate after the CLK divider.
2
Wake-up time is dependent on the value of the decoupling capacitors.
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
N – 8
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
N – 7
N – 6
N – 5
N – 4
VIN
CLK+
CLK–
DATA
DCO
t
A
08
54
1-
00
2
Figure 2. CMOS Output Data Timing