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Atmel
ARM-Based Evaluation Kit AT91SAM9N12-EK
数据表
Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 数据表
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AT91SAM9N12-EK
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ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
vii
List of Tables
ARM926EJ-S Technical Reference Manual
Change history .............................................................................................................. ii
Table 2-1
CP15 register summary ............................................................................................ 2-3
Table 2-2
Address types in ARM926EJ-S ................................................................................. 2-4
Table 2-3
CP15 abbreviations ................................................................................................... 2-5
Table 2-4
Reading from register c0 ........................................................................................... 2-7
Table 2-5
Register 0, ID code ................................................................................................... 2-8
Table 2-6
Ctype encoding ......................................................................................................... 2-9
Table 2-7
Cache size encoding (M=0) .................................................................................... 2-10
Table 2-8
Cache associativity encoding (M=0) ....................................................................... 2-10
Table 2-9
Line length encoding ............................................................................................... 2-11
Table 2-10
Example Cache Type Register format .................................................................... 2-11
Table 2-11
Control bit functions register c1 ............................................................................... 2-13
Table 2-12
Effects of Control Register on caches ..................................................................... 2-15
Table 2-13
Effects of Control Register on TCM interface .......................................................... 2-16
Table 2-14
Domain access control defines ............................................................................... 2-18
Table 2-15
FSR bit field descriptions ........................................................................................ 2-19
Table 2-16
FSR status field encoding ....................................................................................... 2-20
Table 2-17
Function descriptions register c7 ............................................................................ 2-21
Table 2-18
Cache operations c7 ............................................................................................... 2-22
Table 2-19
Register c8 TLB operations ..................................................................................... 2-25
Table 2-20
Cache Lockdown Register instructions ................................................................... 2-27
Table 2-21
Cache Lockdown Register L bits ............................................................................. 2-28
Table 2-22
TCM Region Register instructions .......................................................................... 2-29
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