Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK 数据表
产品代码
AT91SAM9X35-EK
1127
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
46.7.8 LCD Controller Enable Register
Name:
LCDC_LCDEN
Address:
0xF8038020
Access:
Write
Reset:
0x00000000
• CLKEN: LCD Controller Pixel Clock Enable
0: Writing this field to zero has no effect.
1: When set to one the pixel clock logical unit is activated.
• SYNCEN: LCD Controller Horizontal and Vertical Synchronization Enable
0: Writing this field to zero has no effect.
1: When set to one, both horizontal and vertical synchronization (LCD_VSYNC and LCD_HSYNC) signals are generated.
• DISPEN: LCD Controller DISP Signal Enable
0: Writing this field to zero has no effect.
1: When set to one, LCD_DISP signals is generated.
• PWMEN: LCD Controller Pulse Width Modulation Enable
0: Writing this field to zero has no effect.
1: When set to one, the PWM is enabled.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
PWMEN
DISPEN
SYNCEN
CLKEN