Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK 数据表
产品代码
AT91SAM9N12-EK
690
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
Figure 38-6. Synchronized Period or Duty Cycle Update
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his
software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM
Controller level.
software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM
Controller level.
The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the
enabled channel(s). See
enabled channel(s). See
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note:
Reading the PWM_ISR register automatically clears CHIDx flags.
Figure 38-7. Polling Method
Note:
Polarity and alignment can be modified only when the channel is disabled.
38.6.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding
channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled
by setting the corresponding bit in the PWM_IDR register.
by setting the corresponding bit in the PWM_IDR register.
PWM_CUPDx Value
PWM_CPRDx
PWM_CDTYx
End of Cycle
PWM_CMRx. CPD
User's Writing
1
0
Writing in PWM_CUPDx
The last write has been taken into account
CHIDx = 1
Writing in CPD field
Update of the Period or Duty Cycle
PWM_ISR Read
Acknowledgement and clear previous register state
YES