Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK 数据表
产品代码
AT91SAM9X25-EK
28
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
9.2
Embedded Characteristics
ARM9EJ-S
™
Based on ARM
®
Architecture v5TEJ with Jazelle Technology
Three Instruction Sets
ARM
®
High-performance 32-bit Instruction Set
Thumb
®
High Code Density 16-bit Instruction Set
Jazelle
®
8-bit Instruction Set
5-Stage Pipeline Architecture when Jazelle is not Used
Fetch (F)
Decode (D)
Execute (E)
Memory (M)
Writeback (W)
6-Stage Pipeline when Jazelle is Used
Fetch
Jazelle/Decode (Two Cycles)
Execute
Memory
Writeback
ICache and DCache
Virtually-addressed 4-way Set Associative Caches
8 Words per Line
Critical-word First Cache Refilling
Write-though and Write-back Operation for DCache Only
Pseudo-random or Round-robin Replacement
Cache Lockdown Registers
Cache Maintenance
Write Buffer
16-word Data Buffer
4-address Address Buffer
Software Control Drain
DCache Write-back Buffer
8 Data Word Entries
One Address Entry
Software Control Drain
Memory Management Unit (MMU)
Access Permission for Sections
Access Permission for Large Pages and Small Pages
16 Embedded Domains
64 Entry Instruction TLB and 64 Entry Data TLB
Memory Access
8-bit, 16-bit, and 32-bit Data Types
Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit Instructions Interface
Bus Interface Unit
Arbitrates and Schedules AHB Requests
Enables Multi-layer AHB to be Implemented