Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK 数据表
产品代码
AT91SAM9X25-EK
431
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
30.3 DDRSDRC Module Diagram
Figure 30-1. DDRSDRC Module Diagram
DDRSDRC is partitioned in two blocks (see
):
An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four AHB masters and
integrates an arbiter.
integrates an arbiter.
A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
Memory Controller
Finite State Machine
SDRAM Signal Management
Addr, DQM
Data
Asynchronous Timing
Refresh Management
Refresh Management
DDR-SDR
Devices
Power Management
DQS
ras,cas,we
cke
cke
clk/nclk
odt
DDR-SDR Controller
Interconnect Matrix
Input
Stage
Input
Stage
Input
Stage
Output
Stage
Arbiter
APB
AHB Slave Interface 0
AHB Slave Interface 1
AHB Slave Interface 2
AHB Slave Interface 3
Input
Stage
Interface APB