Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK 数据表

959

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is 
provided by writing the Control Register (ADC_CR) with the START bit at 1. 

The hardware trigger can be selected by the TRGMOD field in the 

 between:



Any edge, either rising or falling or both, detected on the external trigger pin, TSADTRG. 



A continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it finishes the current one



A periodic trigger, which is defined by programming the TRGPER field in the “ADC Trigger Register”

The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest 
conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2.

If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the 
selected signal. Due to asynchronous handling, the delay may vary in a range of 2 MCK clock periods to 1 ADC clock 
period.

Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic 
automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable 
(ADC_CHER) and Channel Disable (ADC_CHDR) Registers permit the analog channels to be enabled or disabled 
independently. 

If the ADC is used with a DMA , only the transfers of converted data from enabled channels are performed and the 
resulting data buffers should be interpreted accordingly.

The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for 
conversions. Sleep Mode is selected by setting the SLEEP bit in the Mode Register ADC_MR. 

The Sleep mode is automatically managed by a conversion sequencer, which can automatically process the conversions 
of all channels at lowest power consumption.

This mode can be used when the minimum period of time between 2 successive trigger events is greater than the startup 
period of Analog-Digital converter (See the product ADC Characteristics section).

When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, 
the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, 
the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account.

The conversion sequencer allows automatic processing with minimum processor intervention and optimized power 
consumption. Conversion sequences can be performed periodically usingthe internal timer (ADC_TRGR register) . The 
periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks 
to the DMA.

The sequence can be customized by programming the Sequence Channel Registers, ADC_SEQR1 and ADC_SEQR2 
and setting to 1 the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific order of channels and 
can program up to 12 conversions by sequence. The user is totally free to create a personal sequence, by writing 
channel numbers in ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be written in any sequence, 
channel numbers can be repeated several times. Only enabled sequence bitfields are converted, consequently to 
program a 15-conversion sequence, the user can simply put a disable in ADC_CHSR[15], thus disabling the 16THCH 
field of ADC_SEQR2.

If all ADC channels (i.e. 12) are used on an application board, there is no restriction of usage of the user sequence. But 
as soon as some ADC channels are not enabled for conversion but rather used as pure digital inputs, the respective 
indexes of these channels cannot be used in the user sequence fields (ADC_SEQR1, ADC_SEQR2 bitfields). 

trigger

start

delay