Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
111
32072H–AVR32–10/2012
AT32UC3A3
11.6.3
Non-Maskable Interrupt
The NMI supports the same features as the external interrupts, and is accessed through the
same registers. The description in
same registers. The description in
should be followed, accessing the NMI bit
instead of the INTn bits.
The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution
mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled
by accessing the registers in the EIC.
mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled
by accessing the registers in the EIC.
11.6.4
Asynchronous Interrupts
Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC reg-
ister. This will route the interrupt signal through the asynchronous path of the module. All edge
interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is config-
ured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted
as low level, and a one in EDGE.INTn will be interpreted as high level.
ister. This will route the interrupt signal through the asynchronous path of the module. All edge
interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is config-
ured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted
as low level, and a one in EDGE.INTn will be interpreted as high level.
EIC_WAKE will be set immediately after the source triggers the interrupt, while the correspond-
ing bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of
CLK_SYNC. Please refere to
ing bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of
CLK_SYNC. Please refere to
for details.
When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike
on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be
updated on the first rising edge of CLK_SYNC.
on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be
updated on the first rising edge of CLK_SYNC.
Figure 11-4. Timing Diagram, Asynchronous Interrupts
11.6.5
Wakeup
The external interrupts can be used to wake up the part from sleep modes. The wakeup can be
interpreted in two ways. If the corresponding bit in IMR is one, then the execution starts at the
interrupt handler for this interrupt. If the bit in IMR is zero, then the execution starts from the next
instruction after the sleep instruction.
interpreted in two ways. If the corresponding bit in IMR is one, then the execution starts at the
interrupt handler for this interrupt. If the bit in IMR is zero, then the execution starts from the next
instruction after the sleep instruction.
EXTINTn/NMI
CLK_SYNC
ISR.INTn:
rising EDGE or high
LEVEL
EIC_WAKE:
rising EDGE or high
LEVEL
EXTINTn/NMI
CLK_SYNC
ISR.INTn:
rising EDGE or high
LEVEL
EIC_WAKE:
rising EDGE or high
LEVEL