Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
174
32072H–AVR32–10/2012
AT32UC3A3
Figure 14-6. NAND Flash Signal Multiplexing on EBI Pins
14.6.6.1
NAND Flash signals
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. The user should note
that any bit on the EBI address bus can also be used for this purpose. The command, address or
data words on the data bus of the NAND Flash device are distinguished by using their address
within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy
(R/B) signals are connected to I/O Controller lines. The CE signal then remains asserted even
when NCSx is not selected, preventing the device from returning to standby mode.
driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. The user should note
that any bit on the EBI address bus can also be used for this purpose. The command, address or
data words on the data bus of the NAND Flash device are distinguished by using their address
within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy
(R/B) signals are connected to I/O Controller lines. The CE signal then remains asserted even
when NCSx is not selected, preventing the device from returning to standby mode.
Figure 14-7. NAND Flash Application Example
Note:
The External Bus Interfaces is also able to support 16-bits devices.
SMC
NandFlash
Logic
NCS[2]/[3]
NRD
NWR0_NWE
NANDOE
NANDWE
EBI
EBI
NCS[2/3]
Or I/O line
I/O line
DATA[7:0]
ADDR[22]
ADDR[21]
ALE
CLE
AD[7:0]
NOE
NWE
CE
R/B
NandFlash
NANDOE
NANDWE