Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
234
32072H–AVR32–10/2012
AT32UC3A3
16.8.2
Refresh Timer Register
Register Name:
TR
Access Type:
Read/Write
Offset:
0x04
Reset Value:
0x00000000
• COUNT[11:0]: Refresh Timer Count
This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst
is initiated.
The value to be loaded depends on the SDRAMC clock frequency (CLK_SDRAMC), the refresh rate of the SDRAM device and
the refresh burst length where 15.6µs per row is a typical value for a burst of length one.
To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued
and no refresh of the SDRAM device is carried out.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
COUNT[11:8]
7
6
5
4
3
2
1
0
COUNT[7:0]