Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD 数据表
产品代码
AT32UC3A3-XPLD
238
32072H–AVR32–10/2012
AT32UC3A3
16.8.5
Low Power Register
Register Name:
LPR
Access Type:
Read/Write
Offset:
0x10
Reset Value:
0x00000000
• TIMEOUT: Time to Define when Low Power Mode Is Enabled
• DS: Drive Strength (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be
set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its DS parameter value is updated before entry in self refresh mode.
• TCSR: Temperature Compensated Self Refresh (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to set the refresh interval during self refresh mode depending on the
temperature of the low power SDRAM. This parameter must be set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its TCSR parameter value is updated before entry in self refresh mode.
• PASR: Partial Array Self Refresh (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode. This parameter must be set according to the
SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its PASR parameter value is updated before entry in self refresh mode.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
TIMEOUT
DS
TCSR
7
6
5
4
3
2
1
0
-
PASR
-
-
LPCB
TIMEOUT
Time to Define when Low Power Mode Is Enabled
0
The SDRAMC activates the SDRAM low power mode immediately after the end of the last transfer.
1
The SDRAMC activates the SDRAM low power mode 64 clock cycles after the end of the last transfer.
2
The SDRAMC activates the SDRAM low power mode 128 clock cycles after the end of the last transfer.
3
Reserved.